The present invention relates to differential amplifier circuits and more particularly to a low skew design for a differential amplifier.
The transition times of low-to-high and high-to-low transitions from the output side of the differential amplifier (see FIG. 1) are significantly different. At high frequencies, this difference can be relatively large. The output of the differential stage transitions from VCC (supply voltage) for a high level to a VDS drop above the tail voltage for a low level. Since the tail voltage changes over operating conditions, the skew of the output buffer changes when a ground referenced ratioed inverter is used for receiving the output of the differential amplifier stage.
FIG. 1 shows a typical differential amplifier and gated output inverter circuit combination 100. A differential amplifier includes inputs IN and IN-bar, and an output node OUTBI, as well as a bias switch input BIAS. The differential amplifier includes N-channel transistors M0 and M5 for receiving the IN and IN-bar signals, an active load including P-channel transistors M12 and M14 for providing the OUTBI output signal, N-channel transistor M32 for receiving the BIAS voltage and supplying the tail current, and cascode N-channel transistor M6. The TAIL node is shown as the junction between transistors M0, M5, and M32. The output inverter comprises P-channel transistor M48 and N-channel transistor M58 in a known inverter configuration. The output N1 of the switched inverter is buffered through serially coupled inverter stages 12, 13, and 14 to provide the circuit output OUTB. Note in FIG. 1 that the source of N-channel transistor M58 is coupled to ground.
What is desired therefore is a low skew design for a differential amplifier that significantly reduces the problem with the prior art differential amplifier design described above but keeping any additional circuitry to an absolute minimum.